A quantitative architecture study using SimpleScalar to optimize cache, branch prediction and pipeline design under a strict 512-byte hardware budget.
A comprehensive SimpleScalar-based evaluation framework built to answer a concrete engineering question: how do cache hierarchy, branch prediction strategy and pipeline configuration each contribute to superscalar processor performance, and what is the best possible processor achievable under a hard 512-byte memory constraint? The study spans SPEC95 benchmarks with markedly different memory behavior, giving the conclusions real generality rather than tuning to a single workload.
The evaluation is organized into five phases — cache hierarchy analysis, branch predictor comparison, pipeline parameter sweeps, constraint-based processor design, and a Python automation layer that turns raw simulator text output into structured performance reports.
Diminishing cache returns made it hard to justify hardware spend: ijpeg improved ~39% from smallest to largest cache, but most of that gain arrived by the Medium tier.
Used the Medium-tier data point as the real design target rather than chasing the theoretical maximum, freeing budget for the instruction cache instead.
Longer branch-history registers in the Two-Level Adaptive predictor introduced history aliasing that degraded accuracy rather than improving it.
Benchmarked multiple history widths directly instead of assuming 'longer is better', and selected the width with the best measured direction accuracy.
Out-of-order execution alone cut execution cycles by roughly 55% versus in-order — the single largest lever in the entire study — while the Bimodal predictor already exceeded 99% direction accuracy on ijpeg with a comparatively small BTB. The final constrained design allocated the majority of its 512-byte budget to the instruction cache, which produced the largest improvement under the memory ceiling.